Cost-Efficient Approximation for Magnitude of a Complex Signal (2024)

1. Introduction

For digital baseband signal processing, magnitude calculation for a complex signal is vital to achieve magnitude detection, automatic gain control (AGC), channel estimation, etc. Magnitude calculation is achieved in the works [1,2,3,4,5] using a magnitude detector. The studies [6,7,8,9,10,11] showed that magnitude calculation is carried out to achieve amplitude detection in AGC. Additionally, magnitude calculation is employed to achieve channel estimation in digital baseband receivers [12].

In general, magnitude calculation can be achieved by three approaches, such as the direct method used in [3,6,7,8,9], $α$ Max + $β$ Min used in [1,2] and the COordinate Rotation DIgital Computer (CORDIC) used in [4,5]. It is worth noting that a cost-efficient approach is presented to replace the direct-method, $α$ Max + $β$ Min and CORDIC, and to be used in AGC design [10,11] as well as channel estimations [12]. Importantly, the cost-efficient approach with a pre-biased (or a pre-scaled) factor was first applied to the channel estimation of a baseband receiver [12]. However, neither a signal model nor a mathematical analysis of the cost-efficient approach were provided in [10,11,12].

In this paper, both a signal model and a mathematical analysis of the presented approach with a pre-biased (or a pre-scaled) factor are derived to provide evidence that it is reasonable and inexpensive to carry out the calculation of a complex magnitude. In addition, a numerical simulation and the hardware complexity show that the presented approach is indeed a cost-efficient method for determining the approximate magnitude of a complex signal.

This paper is organized as follows: The conventional approaches to magnitude calculation are reviewed in Section 2. The signal model and the mathematical analysis of the cost-efficient approximation are described in Section 3. The numerical evaluation is shown in Section 4. Case studies and performance comparisons are described in Section 5 and Section 6, respectively. Finally, the conclusions are given in Section 7.

2. Review of ConventionalApproaches

In view of a complex signal x, the direct method for calculating the complex signal magnitude r [13] is expressed as

$r = \sqrt{a^{2} + b^{2}}$

(1)

where a and b are the real and imaginary parts of the complex signal x, respectively. Obviously, Equation (1) is an inefficient approach since it is composed of two operations of multiplication, one operation of addition and one operation of calculating the square-root.

On the other hand, it is well known that $α$ Max + $β$ Min [3,14,15] and CORDIC [4,16] can be applied to calculate the complex signal magnitude. The $α$ Max + $β$ Min approach is easily achieved by binary-shift and addition operations [17] and, therefore, its approximate magnitude ${\hat{r}}_{1}$ is given as

${\hat{r}}_{1} \approx α \cdot Max + β \cdot Min$

(2)

where $α$ and $β$ would be 1 and $\frac{1}{2}$ , 1 and $\frac{1}{4}$ , 1 and $\frac{3}{8}$ , $\frac{15}{16}$ and $\frac{15}{32}$ [15], etc. Additionally, Max = $m a x (| a |, | b |)$ and $Min = m i n (| a |, | b |)$ , where $| \cdot |$ is an absolute-value operation for a real number. In summary, the precision of the $α$ Max + $β$ Min approach is determined by the selection of $α$ and $β$ .

The CORDIC algorithm is a variety of computations using iterative operation. The vectoring mode with circular rotation of the CORDIC algorithm [16] can be used to calculate the complex signal magnitude and is given as

$\begin{matrix} a_{i + 1} & = & a_{i} - d_{i} \cdot b_{i} \cdot 2^{- i} \\ b_{i + 1} & = & b_{i} + d_{i} \cdot a_{i} \cdot 2^{- i} \\ c_{i + 1} & = & c_{i} - d_{i} \cdot e_{i} \end{matrix}$

(3)

where i denotes the iteration number. $d_{i} = - s i g n (b_{i})$ and $e_{i} = t a n^{- 1} (2^{- i})$ , where $s i g n (\cdot)$ is defined to be −1 or 1 depending on whether the argument is negative or positive, respectively. For $a_{0} = a$ , $b_{0} = b$ and $c_{0} = 0$ , after N iterations, the CORDIC outputs are given as

$a_{N} \approx K \cdot \sqrt{a^{2} + b^{2}}, b_{N} \approx 0 and c_{N} \approx t a n^{- 1} (b / a)$

(4)

where K is equivalent to $\prod \sqrt{1 + 2^{- 2 i}}$ and converges to 1.6467. It is clear that the complex signal magnitude ${\hat{r}}_{2}$ of the CORDIC approach can be obtained as follows:

${\hat{r}}_{2} \approx \frac{1}{K} \cdot a_{N}$

(5)

In order to minimize the hardware complexity in Equation (5), $\frac{1}{K}$ can be approximated to 0.60725, which is easily achieved with the shift-and-add operation as $\frac{1}{2} \cdot (1 + 2^{- 2}) \cdot (1 - 2^{- 5}) \cdot (1 + 2^{- 8}) \cdot (1 - 2^{- 10})$ [18]. It is important that the precision of the CORDIC algorithm is proportional to the number of iterations. In other words, its outcome requires extra latencies resulting from more iterative numbers.

3. Signal Model of Cost-EfficientApproximation

For a complex signal $x = a + j b$ , its Cartesian coordinate representation is illustrated in Figure 1a, where a and b are the real and imaginary parts of the complex signal x, respectively. The real and imaginary parts of the complex signal can be used to express the x- and y-axes in a Cartesian coordinate system, individually. In addition, r is a distance from the coordinate point x to the origin and also represents the magnitude of the complex signal x, as described in Equation (1). Apparently, the connection between x, a and the origin takes the shape of a triangle $▵ x a 0$ .

Based on the Triangle inequality [19], the inequality of the triangle $▵ A B C$ , as shown in Figure 1b, is given as

$\bar{A C} \leq \bar{A B} + \bar{B C}$

(6)

Similarly, the triangle $▵ x a 0$ , as depicted in Figure 1a, has the same characteristic as that described in

$r \leq | a | + | b |$

(7)

where $| \cdot |$ represents an absolute value of a real number. Equation (7) indicates that the complex signal x would be located at any quadrant. Without loss of generality, the magnitude of a complex signal x can be reformulated as

${\hat{r}}_{3} \approx λ \cdot (| a | + | b |)$

(8)

4. NumericalEvaluation

In order to evaluate the performances of various magnitude estimations, we use two types of signals, which are the signal around the unit circle and the random signal, to examine the related performance indexes, including the maximum absolute error and the mean square error (MSE). The evaluated errors of various estimations are compared with the direct method as described in (1). All numerical evaluations are modeled by MATLAB with floating-point format, and the results are illustrated in Table 1.

Unit Circle: The signal located on a unit circle is definitely a complex format, which means that the magnitude of the complex signal is equivalent to one. It is easy to examine the related performance indexes. Magnitude evaluation on the unit circle for various methods is shown in Figure 2. For the CORDIC approach constructed by using five iterations, the MSE is almost the same as that of the direct method. Regarding the $α$ Max + $β$ Min approach, both the maximum absolute error and the MSE of $α = \frac{15}{16}$ and $β = \frac{15}{32}$ are lower than those of $α = 1$ and $β = \frac{3}{8}$ . The MSEs of $α = \frac{15}{16}$ and $β = \frac{15}{32}$ , as well as $α = 1$ and $β = \frac{3}{8}$ , are about −29 and −26 dB, respectively. In view of the proposed efficient approach, the MSE is around −20 dB with a pre-scaled factor of 2 dB.
Random Signal: Assuming a complex signal sample $x_{n} = a_{n} + j b_{n}$ , where n is the sample index, both $a_{n}$ and $b_{n}$ are Gaussian random variables with zero-mean. For the numerical evaluation, the $w g n (\cdot)$ function [20] of MATLAB is employed to generate the random signal samples, and the number of evaluated complex signal samples $x_{n}$ is larger than 5 × $10^{6}$ . Additionally, the maximum signal power of the random signal samples is normalized to 1. Similarly, the MSE of CORDIC is identical to that of the direct method. The MSEs of $α = \frac{15}{16}$ and $β = \frac{15}{32}$ , as well as $α = 1$ and $β = \frac{3}{8}$ , are around −42 and −39 dB, respectively. For the proposed efficient approach, the MSE is approximately −33 dB with a pre-scaled factor of 2 dB.
In summary, although the accuracy of the proposed efficient approach is not the best compared with the other approaches, the MSE for the random signal can reach around −33 dB, which is acceptable for this application [12]. According to the result shown in (9), the deviation between the direct method and the efficient approach is definitely less than or equivalent to 3 dB. Consequently, the pre-biased or pre-scaled factor of the proposed efficient approach can be 2∼3 dB, which is determined by the application.

5. CaseStudy

5.1. Amplitude Detector of Digital AGC (DAGC) for Wi-Fi Systems

In order to provide a high signal-to-noise (SNR) signal for further digital baseband signal processing such as coarse/fine symbol boundary detection, coarse/fine carrier frequency offset (CFO) estimation, coarse/fine sampling clock offset (SCO) estimation and channel estimation, it is crucial to employ DAGC and voltage gain amplification (VGA), driving the received signal close to the full-scale level of an analog-to-digital converter (ADC).

Without loss of generality, an IEEE 802.11n 2 × 2 Wi-Fi system, as shown in Figure 3a, is adopted as a test vehicle to evaluate DAGC using the cost-efficient approximation of complex signal amplitude. In addition, the DAGC architecture is illustrated in Figure 3b. Based on the test evaluation, it easily extends to more antenna combinations. A physical layer convergence procedure (PLCP) header with a mixed-format (MF) high-throughput (HT) packet structure is illustrated in Figure 4, where the PLCP is composed of non-HT (legacy) training fields and HT training fields. In the legacy short training field (L-STF), the coarse tuning of DAGC has to be carried out before coarse symbol boundary detection and coarse CFO estimation. In the following legacy long training field (L-LTF), HT-STF, HT-LTF and HT data, the fine tuning of DAGC will be continued to maintain the received signal level.

A MATLAB program is developed to model the front end of a 2 × 2 multiple-input–multiplie-output (MIMO) system for evaluating DAGC operation and reliability. The channel model is produced by the MATLAB function wlanTGnChannel [20], and the related parameters are described as follows:

Delay profile model and root-mean-square (RMS) delay spread: The delay profile of model-B with RMS delay spread of 15 ns.
Maximum delay: 80 ns.
Number of clusters: 2.
Number of taps: 9.
Number of antennas: 1 × 1 for single-input–single-output (SISO) channel in legacy training field, and 2 × 2 for MIMO channel in HT training field.
Distance between transmitter and receiver: 15 m.

The other parameters of wlanTGnChannel are set to default. According to Figure 3b and Equation (8), the amplitude detector ${\hat{r}}_{n}$ of DAGC can be obtained as follows:

${\hat{r}}_{n} = λ (| y_{n, R} | + | y_{n, I} |)$

(11)

where $y_{n, R}$ and $y_{n, I}$ are the real and imaginary parts of the received signal $y_{n}$ . The integral and down are fulfilled using the moving-sum average, where the lengths of the moving sum for STF and LTF are 16- and 32-sample, respectively. The ideal reference amplitudes $V_{r e f}$ for STF and LTF are equivalent to 0.1086 and 0.1075, individually. For the proposed approach, as derived in Equation (11), the reference amplitudes for STF and LTF are equal to $V_{r e f, S}$ = 0.1185 and $V_{r e f, L}$ = 0.1340. Consider the derivation of Equation (11); both $λ_{S}$ and $λ_{L}$ for SFT and LTF are 0.92 and 0.8, respectively. It is important that the signal power of the ADC output has to be unified and maintained close to the full-scale level of ADC by the DAGC tracking loop. Consequently, both $λ_{S}$ and $λ_{L}$ for SFT and LTF can be set to 1.0 since the DAGC loop can be continually tracked to satisfy the amplitude references such as $V_{r e f, S}$ and $V_{r e f, L}$ .

Without loss of exactness, L-SIG and HT-SIG are ignored in numerical evaluation. The simulation results for the signal-to-noise ratio (SNR) = 16 dB are shown in Figure 5, Figure 6 and Figure 7, where both vertical dashed lines express the signal transition from L-LTF to HG-STF. Regardless of legacy and HT training fields, the gain ratio for SISO between the ideal, as described in Equation (1), and the proposed approach, as derived in Equation (11), is than 0.1 dB, which means that the signal power deviation, as shown in Figure 5b, can be ignored since the deviation is much less than the ADC tolerance of 1 bit. Similarly, the gain ratio and the signal power deviations, as illustrated in Figure 6b and Figure 7b for Rx-1 and Rx-2, are 0.12 and 0.3 dB, and 0.27 and 0.32 dB, respectively. The signal power deviations for SISO, Rx-1 and Rx-2 are 0.1, 0.27 and 0.32 dB, respectively. It can be concluded that the proposed approach, as described in Equation (11), has the same performance compared with Equation (1) since the signal power deviation is much less than that of the ADC tolerance of 1 bit.

5.2. Golay-Correlator Window-Based Cancellation (GC-WNC) Equalization Technique

The approximate magnitude calculation for a complex signal, as derived in (10), was applied to GC-WNC equalization [12] for orthogonal frequency-division multiplexing (OFDM) and a single-carrier (SC) mode baseband inner receiver.

The GC-WNC equalization technique is a cooperative scheme in the time and frequency domains to combat the multipath effect in non-line-of-sight (NLOS) and LOS channels for OFDM/SC mode baseband inner receiver over 60 GHz environment for IEEE 802.15.3c [21] and 802.11ad [22]. The technique is composed of GC, WNC and frequency-domain equalization (FDE), where GC and WNC are achieved in the time domain and FDE is fulfilled on each subchannel in the frequency domain.

The GC is employed to estimate the channel impulse response (CIR) of the multipath fading channel in the time domain. However, the estimated CIR has some small-peak samples (see Figure 2 in [12]) that lead to an imperfect estimation of the channel frequency response (CFR) (see Figure 3 in [12]) by transferring the estimated CIR from the time domain to the frequency domain. As a result, the system performance is severely degraded since all of the FDE coefficients are obtained from the defective CFR. In order to minimize the estimation error between the ideal and the estimated CFR, the WNC is employed to remove the small-peak samples of the estimated CIR and further enhance the system performance. The small-peak samples of the estimated CIR can be replaced by zero iff the magnitude of the small-peak samples is less than a threshold value $W_{t h}$ . For the low-hardware-complexity issue, Equation (10) can be used to obtain the approximate magnitude of the small-peak samples, and the pre-biased factor can be merged into the threshold value $W_{t h}$ .

The design criterion of the WNC approach is based on the system SNR degradation induced by an estimation error of less than 0.25 dB. Therefore, the signal power of each removed small-peak sample has to be at least 12 dB less than that of AWGN, which means that the removed small-peak samples of 12 dB lower than AWGN can be viewed as a part of AWGN. It is obvious that the removed small-peak samples are too tiny to affect the CFR estimation. For the normal calculation, the threshold value $W_{t h}$ for 64 QAM with an SNR of 26 dB has to be less than or equivalent to −38 dB, i.e., $W_{t h} \leq 0.0126$ . Based on the numerical evaluation, as described in the previous section, and the system simulation, we choose a 3 dB deviation as the pre-biased factor described in Equation (10) [12]. Furthermore, the 3 dB pre-biased factor can be merged into the threshold value of $W_{t h}$ . To effortlessly conduct a comparison between the approximate magnitude of the estimated CIR and the threshold value, the threshold value is considered to be a power of two. As a consequence, $W_{t h} = 2^{- 6}$ $(= 0.015625$ ) is used for compensating the induced error.

6. Comparison andDiscussion

Considering the occupied area and the power consumption in VLSI implementation for various approaches, the related hardware architectures, as illustrated in Figure 8, are obtained by a 40 nm CMOS general process (GP) with a supply voltage of 0.9 V and an operating clock of 500 MHz, namely, a timing constraint of 2 ns. All of the hardware cells are from DesignWare library [23]. In order to conduct a fair comparison, both the input and output for the related hardware architectures are 20 bits, which means that the real and imaginary parts are 10 bits, individually. The performance evaluations, such as the occupied area and power, for various hardware architectures are extracted from the synthesis reports using Synopsys Design Complier, and further illustrated in Table 2. In addition, both Max |error|% and MSE are the evaluation results from the MATLAB simulation, where the test patterns are the same as those of the previous random signal and quantized as finite wordlength patterns. The related descriptions for the hardware architectures and the performance evaluations are listed below.

Direct method: The hardware architecture of (1) is depicted in Figure 8a, where DW_square and DW_sqrt are DesignWare IPs [23] and perform square and the square-root calculations for a real number, respectively. Both the maximum absolute error and MSE are the smallest of all the approaches. However, both the area and power are the second largest compared with the other approaches.
$α$ Max + $β$ Min approach: The hardware architecture of (2) is illustrated in Figure 8b, where $α$ and $β$ are equivalent to $\frac{15}{16}$ and $\frac{15}{32}$ , respectively. It is worth noting that the related hardware architectures for $| a |$ , $| b |$ and $| a | \geq | b |$ are not shown in Figure 8b. The MSE is around −43 dB.
CORDIC algorithm: Due to the timing constraint of 2 ns, the CORDIC computation can not be achieved using an iterative operation. Therefore, the hardware architecture of (4) is shown in Figure 8c, including the five stages of the CORDIC process element (PE) and an output stage. In order to make a fair comparison, only $a_{i + 1}$ and $b_{i + 1}$ , as described in (4), are obtained in the design template since $c_{i + 1}$ is irrelative to find ${\hat{r}}_{2}$ . The hardware architecture of the CORDIC PE is sketched in the ith stage, as illustrated in the middle of Figure 8c. To reduce the hardware complexity and preserve the 10-bit resolution at the square-root output, $\frac{1}{K}$ is revised as 0.607421875, which is fulfilled by $\frac{1}{2} \cdot [(1 + 2^{- 2}) - 2^{- 5} \cdot (1 + 2^{- 3})]$ at the output stage. Consequently, the MSE is identical to that of the direct method. Although CORDIC has merely five PEs, both its area and power are the largest compared with the other approaches.
Proposed type-1 approach: The hardware architecture of the proposed efficient approach, as described in (10), is illustrated in Figure 8d. The absolute-value operation of a negative number is implemented by a 2’s complement operation, which is composed of an operation of a 1’s complement and the operation of a plus-one. The plus-one operation is fulfilled by the addition of the most significant bit (MSB) of the negative number, such as $a [MSB]$ and $b [MSB]$ in Figure 8d, since $a [MSB]$ and $b [MSB]$ are the sign bits. Both selections ${SEL}_{a}$ and ${SEL}_{b}$ of the multiplexers (MUXs) are also equivalent to $a [MSB]$ and $b [MSB]$ , respectively, and are used to select the input positive number or the absolute value of the input negative number. Finally, the MSE is around −33 dB.
Proposed type-2 approach: In order to further save on hardware costs in the proposed type-1 approach, the absolute-value operation is simplified as a 1’s complement operation for the negative number. Obviously, without a plus-one operation, the absolute value is viewed as precision loss that can be merged into the quantized error. It is worth noting that the quantized error due to the 1’s complement is acceptable since it is below −54 dB. Therefore, the MSE is the same as that of the type-1 approach. The hardware architecture of the proposed type-2 approach is illustrated in Figure 8e. Similarly, both selections ${SEL}_{a}$ and ${SEL}_{b}$ of MUXs are the same as those of the proposed type-1 approach.
See Also
Chapter 8, Complex Numbers and Additional Plots Video Solutions, MATLAB Programming for Engineers | Numerade

According to the results shown in Table 2, the related comparisons, including area, power and performance, are summarized as follows:

Although the performance indexes of the proposed efficient approach are not the best, the MSE for the proposed type-1 and -2 approaches can reach around −32.7 dB. Additionally, the quantized error induced by the 1’s complement of the type-2 approach is −54.2 dB, which is lower than the MSE of 21.5 dB. From an MSE point of view, the quantized error caused by the 1’s complement operation can be ignored. Consequently, the type-2 approach is an appropriate method in the considered applications [12] since the performance indexes of the type-2 approach are the same as those of the type-1 approach.
The area of the direct method is used as the base area to reveal the hardware cost reduction efficiency $η$ . It is clear that the areas of the CORDIC, $α$ Max + $β$ Min, and type-1 and the type-2 approaches are around 1.08, 0.31, 0.13, and 0.09 times the area of the direct method, respectively.
In fact, the CORDIC approach comprises a variety of computations. Using CORDIC to perform a single operation has no benefits, since the area of CORDIC is the largest compared with the other approaches.

7. Conclusions

In this paper, an efficient approach is presented to acquire the approximate magnitude of a complex signal. A signal model and a mathematical analysis are derived to determine the approximate magnitude of the complex signal with a pre-biased or pre-scaled factor in the design criteria. Based on the deductive results, the pre-biased or pre-scaled factor can be 2∼3 dB, which is determined by the application. Furthermore, the numerical evaluations show that the MSE of the proposed efficient approach for the random signal can reach around −33 dB. In order to save on hardware costs, the absolute value of a negative number for the proposed type-2 approach is simplified as a 1’s complement operation, where precision loss can be viewed as quantized noise and further ignored. The physical implementation results indicate that the areas of the proposed type-1 and -2 approaches are 90.27 and 60.78 mm² with a 40 nm CMOS general process, respectively. The power consumptions of the proposed type-1 and -2 approaches are 34.5 and 29.9 $μ$ W with a supply voltage of 0.9 V and an operating clock of 500 MHz. Therefore, the occupied areas of the proposed type-1 and -2 approaches are only 0.13 and 0.09 times the area of the direct-method, respectively. The presented type-1 and -2 approaches with acceptable MSEs are indeed cost-efficient methods compared with the other considered approaches.

Author Contributions

Conceptualization, methodology, software, validation, formal analysis, investigation, C.-F.W. and M.-T.S.; data curation, writing—original draft preparation, C.-F.W.; writing—review and editing, C.-F.W. and M.-T.S.; supervision, M.-T.S.; project administration, funding acquisition, C.-F.W. and M.-T.S. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported in part by the Ministry of Science and Technology, Taiwan, under grants MOST 110-2221-E-182-064, 110-2221-E-008-100, 110-2622-8-008-004-TA, 109-2221-E-008-073 and 109-2622-8-008-003-TA.

Data Availability Statement

Data are only available on request due to restrictions. The data presented in this study are available on request from the corresponding author.

Acknowledgments

The authors would like to thank the Taiwan Semiconductor Research Institute (TSRI), National Applied Research Laboratories (NARLabs), for their support in using the EDA tools.

Conflicts of Interest

The authors declare no conflicts of interest.

References

Smyk, R.; Czyżak, M. Imroved Magnitude Estimaton of Complex Numbers Using alpha Max and Beta Min Algorithm. Zesz. Nauk. Wydziału Elektrotech.i Autom. Politech. Gdańskiej 2016, 51, 167. [Google Scholar]
Smyk, R.; Czyżak, M. Implementation of Magnitude Calculation of Complex Numbers using Improved Alpha Max plus Beta Min Algorithm. Zesz. Nauk. Wydziału Elektrotech. Autom. Politech. Gdańskiej 2016, 51, 173. [Google Scholar]
Anttila, L.; Lampu, V.; Hassani, S.A.; Campo, P.P.; Korpi, D.; Turunen, M.; Pollin, S.; Valkama, M. Full-Duplexing With SDR Devices Algorithms FPGA Implementation and Real-Time Results. IEEE Trans. Wirel. Commun. 2021, 20, 2205. [Google Scholar] [CrossRef]
Codenie, J.; Wang, X.; Zhi, Q.X.; Vlietinck, J.; Lambrecht, P.; Vandewege, J.; Meyer, K.D.; Trog, W. Implementation of a digital amplitude detector based on the CORDIC Transform. In Proceedings of the 39th Midwest Symposium on Circuits and Systems, Ames, IA, USA, 21 August 1996; Volume 2, p. 860. [Google Scholar] [CrossRef]
Czyżak, M.; Smyk, R. FPGA Computation of Magnitude of Complex Numbers using Modified CORDIC Algorithm. Zesz. Nauk. Wydziału Elektrotech. Autom. Politech. Gdańskiej 2015, 47, 35. [Google Scholar]
Codenine, J.; Wang, X.; Everaert, A.; Lambrecht, P.; Vandewege, J.; Meyer, K.D.; Trong, W.; Vleeshouwer, A.D. 16 QAM burst mode receiver for upstream communication over CATV networks. In Proceedings of the 40th Midwest Symposium on Circuits and Systems, Sacramento, CA, USA, 6 August 1997; p. 573. [Google Scholar] [CrossRef]
Zhang, N.; Wen, Z.; Hou, X.; Wen, W. Digital Automatic Gain Control Design with Large Dynamic Range in Wireless Communication receivers. In Proceedings of the 2017 IEEE 17th International Conference on Communication Technology (ICCT), Chengdu, China, 27–30 October 2017; p. 1402. [Google Scholar] [CrossRef]
Dobreb, D.P.; Neycheva, T.D. Software Automatic Gain Control for Common Mode Interference Stabilization. In Proceedings of the 2020 XXIX International Scientific Conference Electronics (ET), Sozopol, Bulgaria, 16–18 September 2020. [Google Scholar] [CrossRef]
Liang, Y.; Zhao, L.; Tang, Q. Design of High Dynamic AGC Control Model and Signal Processing Algorithm for Software Radio Receivers. In Proceedings of the 2020 IEEE 9th Joint International Information Technology and Artificial Intelligence Conference (ITAIC), Chongqing, China, 11–13 December 2020; p. 1442. [Google Scholar] [CrossRef]
Sobaihi, K.; Hammoudeh, A.; Scammell, D. Automatic Gain Control on FPGA for Software-Defined Radios. In Proceedings of the Wireless Telecommunications Symposium 2012, London, UK, 18–20 April 2012. [Google Scholar] [CrossRef]
Stanko, D.; Sommerkorn, G.; Ihlow, A.; Galdo, G.D. Enable Software-Defined Radios for Real-Time MIMO Channel Sounding. In Proceedings of the 2021 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Glasgow, UK, 17–20 May 2021. [Google Scholar] [CrossRef]
Wu, C.F.; Liu, W.C.; Tsui, C.C.; Liu, C.Y.; Sie, M.S.; Jou, S.J. Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2016, 24, 3323. [Google Scholar] [CrossRef]
Dorf, R.C.; Svoboda, J.A. Introduction to Electric Circuits, 9th ed.; John Wiley & Sons, Inc.: Hoboken, NJ, USA, 2014. [Google Scholar]
Filip, A.E. Linear Approximation to x²+y² Having Equiripple Error Characteristics. IEEE Trans. Audio Electroacoust. 1973, 21, 554. [Google Scholar] [CrossRef]
Lyons, R. Understanding Digital Signal Processing, 3rd ed.; Prentice-Hall: Hoboken, NJ, USA, 2011; p. 679. [Google Scholar]
Parhami, B. Computer Arithmetic: Algorithms and Hardware Designs; Oxford University Press: Oxford, UK, 2000. [Google Scholar]
Allie, M.; Lyons, R. A Root of Less Evil. IEEE Signal Process. Mag. 2005, 22, 93. [Google Scholar] [CrossRef]
Valls, J.; Sansaloni, T.; Passual, A.P.; Torres, V.; Almenar, V. The Use of CORDIC in Software Defined Radios: A Tutorial. IEEE Comm. Mag. 2006, 44, 46. [Google Scholar] [CrossRef]
Leon, S.J. Linear Algebra with Applications, 3rd ed.; Macmillan Publishing Company: New York, NY, USA, 1990. [Google Scholar]
MATLAB Help Center. Available online: https://www.mathworks.com/help/comm/ref/wgn.html (accessed on 30 June 2024).
IEEE Std. 802.15.3c; Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANS) Amendment 2: Millimeter-wave-based Alternative Physical Layer Extension. IEEE Computer Society: Washington, DC, USA, 2009.
IEEE Std. 802.11.ad; Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 3: Enhancements for Very High Throughput in the 60 GHz Band. IEEE Computer Society: Washington, DC, USA, 2012.
Synopsys DesignWare Library—Datapath and Building Block IP. Available online: https://www.synopsys.com/designware-ip/soc-infrastructure-ip/designware-library.html (accessed on 30 June 2024).

Figure 1. (a) Complex signal in Cartesian coordinate system and (b) a triangle ΔABC.

Figure 2. Magnitude evaluation on the unit circle for various methods.

Figure 3. (a) Block diagram of 2 × 2 MIMO system; the other radio frequency (RF) and the baseband processing blocks are not depicted here. (b) DAGC architecture.

Figure 4. The PLCP header with a mixed-format high-throughput packet structure.

Figure 5. (a) The tracking trajectory of VGA gain and (b) the signal power of the moving sum for the ADC output in the legacy training field, where SNR = 16 dB.

Figure 6. (a) The tracking trajectory of VGA gain and (b) the signal power of the moving sum for the Rx-1 ADC output in the HT training field, where SNR = 16 dB.

Figure 7. (a) The tracking trajectory of VGA gain and (b) the signal power of the moving-sum for the Rx-2 ADC output in the HT training field, where SNR = 16 dB.

Figure 8. Various hardware architectures for calculating the complex signal magnitude: (a) direct-method, (b) $α$ Max + $β$ Min approach, where $α = \frac{15}{16}$ and $β = \frac{15}{32}$ , (c) CORDIC approach, (d) the proposed type-1 approach and (e) the proposed type-2 approach.

Table 1. Numerical evaluation for various approaches.

		#CORDIC	$α$ Max + $β$ Min		This Work *Equation (8)
		#CORDIC	$α = 1$ , $β = \frac{3}{8}$	$α = \frac{15}{16}$ , $β = \frac{15}{32}$	This Work *Equation (8)
Unit Circle	Max. \|error\|%	0.23	6.80	6.25	20.57
Unit Circle	MSE × 10⁻³	0.00	2.27	1.20	9.90
Random Signal	Max. \|error\|%	0.19	6.49	4.80	15.70
Random Signal	MSE × 10⁻³	0.00	0.13	0.07	0.55

#: iterations of CORDIC operation; *: The pre-scaled factor of 2 dB.

Table 2. Comparisons of area and power consumption for various approaches, where $α = \frac{15}{16}$ and $β = \frac{15}{32}$ for $α$ Max + $β$ Min approaches.

	Direct Method	#CORDIC	$α$ Max + $β$ Min	Proposed Type-1	Proposed Type-2
Area ( $μ$ m²)	713.74	767.72	218.18	90.27	60.78
powaer ( $μ$ W)	473.2	673.8	131.2	34.8	29.9
$η$	1	1.08	0.31	0.13	0.09
Max \|error\|%	0.23	8.82	4.50	15.91	15.91
MSE × 10⁻³	0.00	0.00	0.05	0.54	0.54

#: 5 stages of CORDIC operation.

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

© 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).